As manufacturing techniques such as a processing technique and a designing technique of an integrated circuit are improve, a size of device has recently been minute. As a result, a system which used to be embodied under a board level now can be embodied in a chip, namely system-on-chip (SoC). However, as many devices are integrated in one chip, a chip size has gradually been enlarged and a wire has relatively been lengthened.
On the other hand, a synchronous designing method using a conventional global clock for designing a chip with high capacity, it is difficult to solve a problem of a timing closure due to a clock skew, jitter and a time delay of wire as clock speed increases. Furthermore, it has been reached to the limit to improve performance of the system due to the increase of power consumption occurred in an additional circuit for assigning a clock.
Therefore, a system design using an asynchronous designing method for overcoming a limitation of improving capability of a synchronous circuit and a problem of power consumption due to a clock driving has been studied widely.
The asynchronous designing method can be an alternative for solving those problems in the aspect of performing a data transmission by a handshake protocol, without using a global clock.
Moreover, as another alternative proposal, a globally asynchronous locally synchronous (GALS) system capable of using advantages of both the synchronous designing method and the asynchronous designing method is being studied recently.
In the case of designing a chip with high capacity by the asynchronous designing method including the GALS system, the handshake protocol is used to transfer data, and the bundled data method is the most general and the easiest way.
FIG. 1 is a timing diagram illustrating an embodiment of transferring one bit data according to the bundled data method using 4-phase handshake protocol.
As shown in FIG. 1, when a valid data value is stabilized in a data transmission unit, if a request signal req is generated, a data receiving unit senses the request signal req, and latches the valid data value, then transmits an acknowledge signal ack to the data transmission unit.
After then, when the request signal req is initialized with a logical value ‘0’ in the data transmission unit, the acknowledge signal ack is also initialized in the data receiving unit, so that the succeeding data can be prepared in the data transmission unit.
During this, the data receiving unit senses the valid data when the request signal req becomes a logical value ‘1’. At that time, the valid data should already be stabilized. Therefore, it should be assumed that there needs to be a time interval between the data and the request signal req. Typically, variation of the request signal req is delayed by inserting a delay component in the request signal req wire.
However, a transmission method assuming a delay time, such as the bundled data protocol, is not proper for designing a chip with high capacity such as a system-on-chip. That is, it is possible to fix a timing assumption between the data signal data and the request signal req only after a routing process of a wire completes, and it is also necessary to insert a delay component for each of many data lines.
In other words, many wires are necessary for transferring data among a number of blocks, and it is impossible to estimate a delay time before the routing step for each of the wires. Accordingly, when the delay time of each wire is different, it causes remarkable increase of designing complexity.
Therefore, in order to solve the aforementioned problem, a data transmission method regardless of a delay time of wire is requested and a dual-rail encoding method and a 1-of-4 data encoding method as a data transmission method regardless of a delay time of wire have been studied.
It will briefly be described about the two aforementioned methods with reference to FIGS. 2 and 3 as follows.
FIG. 2 is an explanatory diagram illustrating one bit data transmission by the dual-rail data encoding method. FIG. 2a is a timing diagram and FIG. 2b is a data value definition table. Data is represented by physically using two wires for valid data ‘0’ and ‘1’.
That is, as shown in the data definition table of FIG. 2b, by using two wires data.t, and data.f, when the data.f is ‘1’, the valid data is ‘0’, and when the data.t is ‘1’, the valid data is ‘1’. Here, if one of the two wires is changed, it means a data arrival. During this, the data receiving unit generates the acknowledge signal ack.
Furthermore, there is a space state positioned between a current data and a succeeding data in order to represent the succeeding data. The space state is represented by ‘0’ for all of the wires data.t and data.f. The data transmission unit confirms the acknowledge signal ack from the data receiving unit for preparing the succeeding data, and transfers the data to the space state.
FIG. 3 is an explanatory diagram illustrating two bits data transmission by the 1 of 4 data encoding method. FIG. 3a is a timing diagram and FIG. 3b is a data value definition table.
Different from the dual-rail data encoding method in FIG. 2, the data transmission method in FIG. 3 represents possible two bits data ‘00’, ‘01’, ‘10’, ‘11’ by changing state of one wire among the four wires.
That is, as described in FIG. 3b, for four wires data0, data1, data2, data3, when the data0 is a logical value ‘1’, the valid data is ‘00’ and when the data1 is a logical value ‘1’, the valid data is ‘01’ When the data 2 and data 3 are logical value ‘1’, respectively, the valid data are ‘10’ and ‘11’, respectively. The 1 of 4 data transmission method also needs the space state as the dual-rail data encoding method and represents the space state when all the four wires are logical value ‘0’.
The data transmission methods aforementioned in FIGS. 2 and 3 do not need the acknowledge signal ack, and variation of data encoded in the space state means a data arrival. According to this, it can be possible to perform a stabilized data transmission regardless of a delay time of wire.
However, the data transmission methods physically need 2N+1 wires for transferring N bit data. It thereby causes remarkable increase of designing complexity due to wires. Especially, a cross talk has bad influence of dropping down a transmission speed under a deep-submicron DSM condition.